
module bram_tx#(
    parameter rd_len = 4096
)(
    input                clk        , //时钟信号
    input                rst_n      , //复位信号
    input                start_rd   ,
    output  reg          rd_ready   ,
    input                rd_ack     ,
    input        [31:0]  start_addr ,
    input                read_en,
    input        [15:0]  data,
    output  reg          adc_en,
    //RAM端口
    output               ram_clk    , //RAM时钟
    input        [31:0]  ram_rd_data, //RAM中读出的数据
    output  reg          ram_en     , //RAM使能信号
    output  reg  [31:0]  ram_addr   , //RAM地址
    output  reg  [3:0]   ram_we     , //RAM读写控制信号
    output  reg  [15:0]  ram_wr_data, //RAM写数据
    output               ram_rst      //RAM复位信号,高电平有效
);

//reg define
reg  [2:0]   flow_cnt;
reg          start_rd_d0;
reg          start_rd_d1;
reg          read_en_d0;
reg          read_en_d1;

//wire define
wire         pos_start_rd;
wire         read_en_start;
//*****************************************************
//**                  main code
//*****************************************************

assign  ram_rst = 1'b0;
assign  ram_clk = clk ;


assign pos_start_rd = ~start_rd_d1 & start_rd_d0;
assign read_en_start = ~read_en_d1 & read_en_d0;


//延时两拍，采start_rd信号的上升沿
always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        start_rd_d0 <= 1'b0;   
        start_rd_d1 <= 1'b0; 
    end
    else begin
        start_rd_d0 <= start_rd;   
        start_rd_d1 <= start_rd_d0;     
    end
end

always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        start_rd_d0 <= 1'b0;   
        read_en_d1 <= 1'b0; 
    end
    else begin
        read_en_d0 <= read_en;   
        read_en_d1 <= read_en_d0;     
    end
end

//根据读开始信号,从RAM中读出数据
always @(posedge clk or negedge rst_n) begin
    if(!rst_n) begin
        flow_cnt <= 3'd0;
        ram_en <= 1'b0;
        ram_addr <= 32'd0;
        ram_we <= 4'b1111;
        adc_en <= 1'b0;
        rd_ready <= 1'b0;
    end
    else begin
        case(flow_cnt)
            2'd0 : begin
                if(pos_start_rd) begin
                    ram_en <= 1'b1;
                    ram_addr <= start_addr;
                    flow_cnt <= flow_cnt + 2'd1;
                    adc_en <= 1'b1;
                    rd_ready <= 1'b0;
                end
            end
            2'd1 : begin
                if(ram_addr - start_addr == rd_len - 2) begin  //数据读完
                    ram_en <= 1'b0;
                    flow_cnt <= flow_cnt + 2'd1;
                    rd_ready <= 1'b1;
                end
                else
                begin
                    if(read_en_start)
                    begin
                        ram_addr <= ram_addr + 32'd2;              //地址累加2
                        ram_wr_data <= data;
                    end
                end
            end
            2'd2 : begin
                ram_addr <= 32'd0; 
                flow_cnt <= 2'd0;
            end
        endcase    
    end
end

endmodule
